`ifndef UDLY
`define UDLY 1
`endif
module mem_model__5(
  mem_port__addr,
  mem_port__wdata,
  mem_port__rdata,
  mem_port__we_n,
  mem_port__ce_n,
  clk,
  rstn
);
//parameter declare
//port declare
input [31:0] mem_port__addr;
input [63:0] mem_port__wdata;
output [63:0] mem_port__rdata;
input mem_port__we_n;
input mem_port__ce_n;
input clk;
input rstn;
//channel declare
//wire declare
logic [63:0] rd_data;
logic [31:0] __addr_t_49;
//port wire declare
wire [31:0] mem_port__addr;
wire [63:0] mem_port__wdata;
logic [63:0] mem_port__rdata;
wire mem_port__we_n;
wire mem_port__ce_n;
wire clk;
wire rstn;
//register declare
reg [63:0] mem[0:255];

//register init and update
reg [63:0] rd_data_dly;
wire [63:0] _rd_data_dly;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    rd_data_dly <= #`UDLY 64'h0;
  end
  else begin
    rd_data_dly <= #`UDLY _rd_data_dly;
  end
end

reg port__ce_n;
wire _port__ce_n;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    port__ce_n <= #`UDLY 1'h0;
  end
  else begin
    port__ce_n <= #`UDLY _port__ce_n;
  end
end

reg port__we_n;
wire _port__we_n;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    port__we_n <= #`UDLY 1'h0;
  end
  else begin
    port__we_n <= #`UDLY _port__we_n;
  end
end

reg [31:0] port__addr;
wire [31:0] _port__addr;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    port__addr <= #`UDLY 32'h0;
  end
  else begin
    port__addr <= #`UDLY _port__addr;
  end
end

reg [63:0] port__wdata;
wire [63:0] _port__wdata;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    port__wdata <= #`UDLY 64'h0;
  end
  else begin
    port__wdata <= #`UDLY _port__wdata;
  end
end

//assign logic
assign _port__ce_n /* 37 */ = mem_port__ce_n /* 37 */ ;
assign _port__we_n /* 38 */ = mem_port__we_n /* 38 */ ;
assign _port__addr /* 39 */ = mem_port__addr /* 39 */ ;
assign _port__wdata /* 40 */ = mem_port__wdata /* 40 */ ;
assign __addr_t_49 /* 45 */ = mem_port__addr /* 45 */ ;
assign rd_data /* 46 */ = ((!mem_port__ce_n)&&mem_port__we_n /* 47 */ )?(mem[__addr_t_49] /* 48 */ ):64'h0 /* 50 */  /* 49 */ ;
assign _rd_data_dly /* 52 */ = rd_data /* 52 */ ;
assign mem_port__rdata /* 55 */ = rd_data_dly /* 55 */ ;
//register update logic
always_comb begin /* 41 */ 
  if((!port__ce_n)&&(!port__we_n)) begin  /* 42 */ 
  mem[port__addr] = port__wdata /* 43 */ ;
  end
end

//cell instance
endmodule
